Pseudo-NMOS logic having a feedback controller

ABSTRACT

A pseudo-NMOS circuit includes a load PFET electrically connected between a power supply and an output node, and an NFET circuit having a plurality of inputs connected between the output node and ground. A feedback PFET is electrically connected between the power supply and the output node, in parallel with the load PFET, and is controlled by a signal at the output node of the pseudo-NMOS circuit.

FIELD OF INVENTION

[0001] The present invention generally relates to CMOS logic circuits,and more particularly to a pseudo-NMOS logic circuit with numerousinputs.

BACKGROUND

[0002] A pseudo-NMOS logic implemented in a CMOS circuit typicallyincludes a load PFET (PMOS) with its gate tied to ground (GND), so thatthe load PFET is always ON. The source and the drain of the load PFETare connected between the supply voltage (VDD) and a “pulldown” NFETtree or circuit, respectively. A typical conventional pseudo-NMOS logicimplemented in a CMOS circuit is shown in FIG. 3, where Z is the outputnode of the pseudo-NMOS logic. The pulldown NFET tree implements thedesired equations of the pseudo-NMOS logic. A conventional pseudo-NMOSlogic implementing a NOR equation, for example, is shown in FIG. 4.

[0003] In a wide “fan-in” implementation of the pseudo-NMOS logic havingnumerous inputs to the pulldown tree, such as the NOR circuit shown inFIG. 4, “leakage” in the NFETs of the pulldown tree becomes a problemwhen the output at the node Z is high. A leakage occurs when there isundesirable current flow from source to drain even when the inputvoltage to the NFETs is zero or near zero. In other words, the NFETs donot act as a perfect switch. Power differential or noise at the inputsto the NFETs exacerbates the leakage problem, which results in noisebeing transmitted to other circuits that are connected to the outputnode Z of the pseudo-NMOS circuit.

[0004] The size (i.e., the width) of the load PFET can be increased tocounter input noise and NFET leakage. In this manner the PFET becomesstronger (i.e., able to drive more current) so that there is less impacton the PFET by the leakage. However, this approach undesirably increasesthe voltage output level (VOL) when the NFETs are turned ON to produce alogical LOW value at the output Z. Alternatively, the size of the NFETscan be decreased. However, this method also results in increasing VOL.

SUMMARY OF THE INVENTION

[0005] In accordance with one embodiment of the present invention, apseudo-NMOS circuit includes a first PFET electrically connected betweena power supply and an output node. An NFET circuit is connected betweenthe output node and ground and has a plurality of inputs. A second PFETis electrically connected between the power supply and the output node,and has a gate which is controlled by a signal at the output node.

DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a circuit diagram of a pseudo-NMOS logic circuit inaccordance with one embodiment of the present invention;

[0007]FIG. 2 is the pseudo-NMOS logic circuit of FIG. 1 implementing alarge high fan-in input NOR gate;

[0008]FIG. 3 is a conventional pseudo-NMOS logic circuit; and, FIG. 4 isa conventional pseudo-NMOS logic circuit of FIG. 3 implementing a highfan-in input NOR gate.

DETAILED DESCRIPTION OF THE INVENTION

[0009] Turning now to FIG. 1, a pseudo-NMOS circuit in accordance oneembodiment of the present invention is indicated generally at 10 andincludes a load PFET (or PMOS) 12 having a gate 14 tied to ground (GND)so that the PFET is always ON. A source 16 of the load PFET 12 isconnected to the supply voltage (VDD), and a drain 18 is connected to a“pulldown” NFET tree or circuit 20 at an output node Z of thepseudo-NMOS circuit 10. The NFET tree 20 is also connected to groundGND. The NFET tree 20 implements the desired equation of the pseudo-NMOSlogic 10 and produces the result at the output node Z.

[0010] A feedback PFET (or PMOS) 22 is also connected between VDD andthe NFET tree 20, parallel to the load PFET 12. A source 24 and a drain26 of the feedback PFET 22 are connected respectively to VDD and theouput node Z, as with the load PFET 12. A gate 28 of the feedback PFET22, however, is connected to an output node FB of an inverter circuit30.

[0011] The inverter circuit 30 includes a PFET (or PMOS) 32 connected toan NFET (or NMOS) 34, with a drain 36 of the PFET 32 connected to adrain 38 of the NFET 34 at the output node FB. A source 40 of the PFET32 is connected to VDD, and a source 42 of NFET 34 is connected to GND.Gates 44, 46 of PFET 32 and NFET 34, respectively, are both commonlyconnected to the output node Z.

[0012] Turning now to FIG. 2, the NFET tree 20 is shown implementing aNOR gate 49, for example, having a plurality of inputs IN_1 to IN_N forcorresponding NFETs 48 that make up the NOR gate. The NFETs 48 areconnected in parallel to each other with their gates 50 tied to thecorresponding inputs IN_1 to IN_N. Drains 52 of the NFETs 48 are allconnected to the output node Z, and sources 54 are connected to GND.

[0013] In operation, when all inputs IN_1 to IN_N transition LOW,voltage at the output node Z rises due to the load PFET 12 conductingcurrent. As the output Z goes HIGH (a logical 1), the inverter circuit30 outputs a LOW at the node FB, since the gates 44, 46 of the PFET 32and NFET 34 are connected to the output node Z. As a result, thefeedback PFET 22 (the gate 28 of which is connected to the output nodeFB) turns ON, thereby aiding in the transition of the output node Z toHIGH. In this manner, the feedback PFET 22 helps to maintain VOH (i.e.,the voltage output level at the output node Z) when the NFETs 48 of theNOR gate 49 are turned OFF to produce a logical HIGH value in thepresence of input noise or GND differentials on the inputs of the NORgate NFETS.

[0014] As one or more of the inputs IN_1 to IN_N to the NFETs 48transitions HIGH, the output node Z transitions to a LOW voltage (alogical zero). The load PFET 12 continues to conduct current, since itsgate 14 is tied to GND. Initially, the feedback PFET 22 will alsoconduct current. However, as the output node Z transitions LOW past thetrip point of the feedback inverter 30, the node FB goes HIGH. Thiscauses the feedback PFET 22 to turn OFF. Those skilled in the art willrecognize that the P-N ratio resulting from the sizing of the PFET 32relative to the NFET 34 of the feedback inverter 30 determines howquickly the feedback PFET will turn OFF. Turning OFF the feedback PFET22 allows the output node Z transition going LOW to occur faster, sincethe pulldown NFET tree 20 (i.e., the NOR gate 49 in the example above)does not have to “fight” with the feedback PFET 22 in an attempt to pullthe output to GND. With the feedback PFET 22 turned OFF, VOL decreasesthereby improving the noise margin (i.e., the range of input voltagethat is interpreted as being a logical LOW) of a circuit (not shown)that receives its input from the output node Z.

[0015] From the foregoing description, it should be understood that animproved circuit topology of a pseudo-NMOS logic has been shown anddescribed which has many desirable attributes and advantages. Inaccordance with one embodiment, a second PFET is connected in parallelto the load PFET and controlled via a feedback signal from the output ofthe pseudo-NMOS circuit. This arrangement results in improvedinput/output noise margin and reduced power consumption.

[0016] While various embodiments of the present invention have beenshown and described, it should be understood that other modifications,substitutions and alternatives are apparent to one of ordinary skill inthe art. Such modifications, substitutions and alternatives can be madewithout departing from the spirit and scope of the invention, whichshould be determined from the appended claims.

[0017] Various features of the invention are set forth in the appendedclaims.

What is claimed is:
 1. A pseudo-NMOS circuit comprising: a first PFETelectrically connected between a power supply and an output node; anNFET circuit connected between said output node and ground and having aplurality of inputs; and, a second PFET electrically connected betweensaid power supply and said output node, said second PFET beingcontrolled by a signal at said output node.
 2. The circuit as defined inclaim 1 further including a control circuit for turning said second PFETON and OFF based on said signal at said output node.
 3. The circuit asdefined in claim 2 wherein said control circuit is electricallyconnected between said power supply and said ground, and has an inputconnected to said output node.
 4. The circuit as defined in claim 3wherein said control circuit is an inverter circuit including a PFETconnected in series to an NFET, and wherein said PFET is electricallyconnected to said power supply, said NFET is connected to said ground,and gates of said PFET and NFET are connected to said output node. 5.The circuit as defined in claim 4 wherein a gate to said second PFET isconnected to a feedback node connecting a drain of said PFET and a drainof said NFET of said inverter circuit.
 6. The circuit as defined inclaim 5 wherein a signal at said feedback node transitions LOW to turnON said second PFET when said signal at said output node is HIGH, andsaid signal at said feedback node transitions HIGH to turn OFF saidsecond PFET when said signal at said output node is LOW.
 7. The circuitas defined in claim 1 wherein a gate of said first PFET is connected tosaid ground, and a gate of said second PFET is connected to a feedbacksignal from said output node.
 8. The circuit as defined in claim 7wherein said second PFET is turned ON when a signal at said output nodeis HIGH, and turned OFF when said signal at said output node is LOW. 9.A pseudo-NMOS circuit for reducing output noise, said circuitcomprising: a load PFET electrically connected between a power supplyand an output node; an NFET circuit having a plurality of inputsconnected between said output node and ground for performing apredetermined function based on signals applied to said inputs andoutputting a signal to said output node; and, a feedback PFETelectrically connected between said power supply and said output nodefor reducing noise at said output node based on said signal at saidoutput node.
 10. The circuit as defined in claim 9 further including afeedback circuit electrically connected to said feedback PFET, whereinsaid feedback circuit sets said feedback PFET to ON when said signal atsaid output node is HIGH, and sets said feedback PFET to OFF when saidsignal at said output node is LOW.
 11. The circuit as defined in claim10 wherein an output of said feedback circuit is LOW when said signal atsaid output node is HIGH, and said output of said feedback circuit isHIGH when said signal at said output node is LOW.
 12. A method forreducing noise at an output of a pseudo-NMOS circuit having a load PFETand an NFET function circuit, said method comprising the steps of:providing a second PFET in parallel with the load PFET between a powersource and the NFET function circuit; and, turning said second PFET ONwhen said output of the pseudo-NMOS circuit is HIGH, and turned OFF saidsecond PFET when said output of the pseudo-NMOS circuit is LOW.
 13. Themethod as defined in claim 12, wherein said second PFET is turned ON andOFF by a feedback circuit connected to an output node of the pseudo-NMOScircuit.
 14. The method as defined in claim 13, wherein said feedbackcircuit is an inverter circuit having an input connected to said outputof the pseudo-NMOS circuit and an output connected to said second PFET.